| 摘要 |
A layout structure of bit line sense amplifier is provided to secure the space for building up the channel of transistor by perpendicularly forming the latch transistor pair of the bit line sense amplifier. A bit line sense amplifier comprises a latch transistor. A gate(22) of the latch transistor is formed into the vertical direction of the bit line(28). The first contact(26) connects the gate and the bit line of the latch transistor. The first contact is formed in an active area(20). A plurality of second contacts(24b,24c) connect the drain region and the bit line of the latch transistor. The third contact /(24a) connects the source region and the bit line of the latch transistor. The latch transistor pair shares the source or the drain region in the active area.
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