| 摘要 |
A static random access memory (SRAM) is provided which includes a plurality of columns and a plurality of cells arranged therein. A voltage control circuit can be used to temporarily reduce a voltage at which power is supplied to cells belonging to a column selected for a write operation. The voltage control circuit may include a first p-type field effect transistor (PFET) and a second PFET. The first PFET may have a conduction path connected between a power supply and the cells belonging to the selected column. The second PFET may have a conduction path connected between the cells belonging to the selected column and ground. Such voltage control circuit may operate in a self-limited manner that avoids overshooting the reduced voltage level. In a variation thereof, a voltage control circuit having first and second NFETs (n-type field effect transistors) can be used to temporarily raise the voltage of a low voltage reference provided to cells of the SRAM.
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