发明名称 Active cycle control circuit and method for semiconductor memory apparatus
摘要 An active cycle control circuit includes a refresh active control signal generation unit that generates a refresh active control signal at the same cycle as a refresh request signal at a timing earlier than the refresh request signal, a refresh standby signal output unit that outputs a refresh standby signal according to a refresh active signal and the refresh request signal, and an active control unit that outputs a row active signal for performing a read cycle according to a read command and outputs the refresh active signal according to the refresh active control signal and the refresh standby signal within the read cycle.
申请公布号 US7515495(B2) 申请公布日期 2009.04.07
申请号 US20060647435 申请日期 2006.12.29
申请人 HYNIX SEMICONDUCTOR INC. 发明人 LEE SANG-KWON
分类号 G11C7/00 主分类号 G11C7/00
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