发明名称 |
Processor for computing a packed sum of absolute differences and packed multiply-add |
摘要 |
A method and apparatus is disclosed that computes multiple absolute differences from packed data and sums each one of the multiple absolute differences together to produce a result. According to one embodiment, a processor includes a decode unit to decode a packed sum of absolute differences (PSAD) instruction having an opcode format to identify a set of packed data operands. The decode unit initiates a sequence of operations on the set of packed data operands in response to decoding the PSAD instruction. An execution unit performs a first operation of the sequence of operations initiated by the decode logic, and a bus provides the execution unit with the set of packed data operands as identified in accordance with the opcode format. |
申请公布号 |
US7516307(B2) |
申请公布日期 |
2009.04.07 |
申请号 |
US20010005728 |
申请日期 |
2001.11.06 |
申请人 |
INTEL CORPORATION |
发明人 |
ABDALLAH MOHAMMAD A.;PENTKOVSKI VLADIMIR |
分类号 |
G06F9/22;G06F7/52;G06F7/533;G06F7/544;G06F9/30;G06F9/302 |
主分类号 |
G06F9/22 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|