| 摘要 |
A latency control circuit of a semiconductor memory device is provided to count clocks for CAS latency after delay corresponding to additive latency to delay a delayed signal corresponding to the CAS latency again and remove an unnecessary count operation before additive latency to reduce current consumption. An additive latency control unit(20) delays an input signal used for data access control correspondingly to preset additive latency to output a delay input signal. A CAS latency command controller(30) counts clock signals from the point of time when the delay input signal is inputted. The delay input signal up to a signal corresponding to the preset CAS latency among the counted signals is delayed to output the delay output signal. A CAS latency controller is comprised of an edge-trigger type counter unit, a toggling controller, and a CAS latency counter unit.
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