| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device increasing speed and scalability. SOLUTION: The device has a plurality of sub-macros 1, 2 connected mutually through a global data line. The respective sub-macros 1, 2 have first and second memory blocks 11, 12 and memory block control circuits 7, 8 arranged between the first and the second memory blocks 11, 12. The memory block control circuits 7, 8 have a DQ buffer block 7 which is connected to the first memory block 11 through a first complementary data line, and connected to the second memory block 12 through a second complementary data line, and a dynamic data shift redundancy circuit block 8 which is connected to the DQ buffer block 7 through a local data line, and recovering the first or the second memory block 11, 12. COPYRIGHT: (C)2009,JPO&INPIT
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