| 摘要 |
A converter circuit is provided herein. In the converter, a voltage converting unit receives an input voltage and outputs an output voltage according to the magnitude of the input voltage by switching operation based on a control clock signal. A comparing circuit generates a power good pulse signal by comparing the output voltage with a reference voltage. A pulse width frequency modulation circuit receives the power good pulse signal and a source clock signal to provide the control clock signal. The pulse width of the source clock signal is varied gradually and the frequency of the source clock signal is also changed during a period that the power good pulse signal remains in the first logic state, and the pulse width frequency modulated source clock signal is output as the control clock signal. |
