发明名称 |
Memory Sense Scan Circuit And Test Interface |
摘要 |
Embodiments of a scannable IO circuit featuring reduced latch count for pipelined memory architectures and test methodology are described. For a pipelined memory system performing at speed tests, the timing sequence for processing a test command comprises a precharge-read-precharge-write sequence for each clock cycle starting with the rising clock edge. The memory circuit utilizing this test command timing sequence comprises a sense amplifier and a single latch. The sense amplifier itself is used as a latch to implements scan functionality for the memory circuit. The memory device is incorporated into an integrated test wrapper circuit that executes back-to-back commands through serial compare operations using integrated scan flip-flop circuits. The test wrapper includes a fanout block and padded address scheme for testing multiple and disparate size memory devices in parallel.
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申请公布号 |
US2009089632(A1) |
申请公布日期 |
2009.04.02 |
申请号 |
US20070863972 |
申请日期 |
2007.09.28 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
MOREIN STEPHEN L. |
分类号 |
G11C29/10;G06F11/26;G06F11/263 |
主分类号 |
G11C29/10 |
代理机构 |
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地址 |
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