| 摘要 |
<p>The invention concerns a high-speed data transfer board, comprising a master part (100) and a slave part (200), characterised in that the master part (100) comprises: - at least two independent network interfaces (110, 110'), to which the following are connected in series: o at least two corresponding independent data filters (120, 120') and o at least two corresponding independent buffer memories (125, 125'); - a single PLB bus (130) that receives the data from said at least two data filters (120, 120') or two corresponding buffer memories (125, 125'); - a microprocessor (140) that, on the basis of received interrupts, controls a DMA engine (150) that downloads selectively the data present on the bus PLB towards a bus host PCIX (160); said slave part (200) comprising circuitry dedicated to the management of secondary and expansion peripherals, in such a way that the board is usable even if it is not installed in a server.</p> |
