METHOD AND SYSTEM FOR TOPOGRAPHY-AWARE RETICLE ENHANCEMENT

摘要

The present invention provides a method and system for improving reticle enhancement calculations during manufacture of an integrated circuit (IC) (308). The reticle enhancement calculations (308) are improved by incorporating post-planarization topography estimates (316). A planarization process of a wafer layer (312) is simulated to estimate the post- planarization topography. RET calculations (308), such as sub-resolution assist feature insertion, optical proximity corrections and phase shifting are then performed based on the post- planarization topography of the wafer layer (306).