| 摘要 |
A pipeline analog-to-digital converter includes a conversion unit receiving an analog input signal and outputting a plurality of digital signals corresponding to quantization values obtained by quantizing the input signal, the conversion unit including a plurality of stages that output the plurality of digital signals, the plurality of stages being connected in a cascade manner, each of the stages receiving a residue analog signal from a previous stage, and a first stage receiving an analog input signal and a digital correction logic receiving the plurality of digital signals, correcting an error, and outputting a digital output signal corresponding to the input signal, wherein a first reference voltage is applied to the plurality of stages, a second reference voltage, which is different from the first reference voltage, is applied to at least one of the plurality of stages, at least one of the plurality of stages includes a plurality of unit capacitors that sample the residue analog signal, and at least one of the plurality of unit capacitors is coupled to the second reference voltage.
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