| 摘要 |
A non-volatile semiconductor memory device includes a floating gate formed above a semiconductor substrate; an erasing gate formed above the floating gate; a control gate formed above a channel region of a surface layer of the semiconductor substrate at a position corresponding to one lateral side of the floating gate and the erasing gate; a first diffusion layer formed on the semiconductor substrate at a position corresponding to another lateral side of the floating gate and the erasing gate; a plug formed above the first diffusion layer, the plug coupled to the first diffusion layer; and a second diffusion layer formed on the semiconductor substrate at a position adjacent to the control gate. With such a device structure, the first diffusion layer and the plug connected thereto are formed in a self-alignment method, thereby contributing to a size reduction of the memory cells. Thus, further miniaturization of the non-volatile semiconductor memory device having an erasing gate may be achieved.
|
