发明名称 |
Analog To Digital Converter |
摘要 |
An ADC, such as a CT SD-ADC, includes a clock generation circuit that produces charging and discharging clock signals such that a settling time for an integrator in the ADC is increased. The clock signals may control a feedback SD-DAC in the CT SD-ADC. The clock signals also may be asymmetric and/or may result in the settling time of the integrator being greater than half the system clock.
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申请公布号 |
US2009085789(A1) |
申请公布日期 |
2009.04.02 |
申请号 |
US20080187632 |
申请日期 |
2008.08.07 |
申请人 |
NANOAMP SOLUTIONS INC. (CAYMAN) |
发明人 |
SCHUUR AXEL;SHEN DAVID H.;SHEN ANN P. |
分类号 |
H03M1/60;G06F3/033;H03M1/12 |
主分类号 |
H03M1/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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