发明名称 SEMICONDUCTOR ELEMENT AND LAYOUT METHOD THEREOF
摘要 A semiconductor device and a lay-out method are provided to prevent the wiring delay by suppressing the capacity between the layout region of the bus wire and the wiring. A semiconductor device comprises the first function block(100), the second function block(200), and a wiring region(300). A bus wire consisting of a plurality of wirings connecting the first function block and the second function block is formed in a wiring region. The first function block and the second function block are the region divided by the function of the semiconductor device. The first function block corresponds to the driver cell region. The second function block corresponds to the electrode pad region. The wiring region is formed in a plurality of wiring layers.
申请公布号 KR20090032943(A) 申请公布日期 2009.04.01
申请号 KR20080064711 申请日期 2008.07.04
申请人 OKI ELECTRIC INDUSTRY CO., LTD. 发明人 YAMATE MICHINO
分类号 H01L21/82;H01L21/3205 主分类号 H01L21/82
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