发明名称 Secure logical vector clocks
摘要 <p>Embodiments include a system 100 for processing logical clock values according to a secure maximum operation. The system 100 may include a communication unit 110 and a processing unit 120. The communication unit 110 may be configured to receive an encrypted first value of a logical clock, send an encrypted blinded difference, receive an encrypted blinded maximum value, and receive a maximum value. The processing unit 120 may be configured to access an encrypted second value of the logical clock, generate the encrypted blinded difference between the first value and the second value, provide an encrypted blinded first value and an encrypted blinded second value in an oblivious transfer protocol, and generate an encrypted maximum value from the encrypted blinded maximum value.</p>
申请公布号 EP2043015(A1) 申请公布日期 2009.04.01
申请号 EP20070018987 申请日期 2007.09.27
申请人 SAP AG 发明人 KERSCHBAUM, FLORIAN;VAYSSIERE, JULIEN, JEAN-PIERRE
分类号 G06F21/72;H04L9/30 主分类号 G06F21/72
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