| 摘要 |
<p>An overlay vernier and a method of formation thereof are provided to improve the property and the reliability of the semiconductor device by improving the precision of the pattern at the process of implementing pattern less than the definition. An etched layer, the first mask layer, and the first photoresist layer are formed on a semiconductor substrate(400). The first photoresist pattern is molded by performing the exposure and development process using the exposure mask for the mother vernier. The first mask layer pattern is molded by etching the first mask layer. The first photoresist pattern is removed. The imbedded spacer is formed in the side wall of the first mask layer pattern. The first mask layer pattern is removed. An etched layer pattern(410a) which defines the mother vernier by etching the etched layer is formed. A planarized intermediate layer(440) is formed on the whole upper unit including etched layer pattern. The second mask layer is formed on the top of the intermediate layer. The second mask layer pattern(450) is formed by using the exposure mask for the daughter vernier.</p> |
