发明名称 |
High speed OTP sensing scheme |
摘要 |
A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
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申请公布号 |
US7511982(B2) |
申请公布日期 |
2009.03.31 |
申请号 |
US20060618330 |
申请日期 |
2006.12.29 |
申请人 |
SIDENSE CORP. |
发明人 |
KURJANOWICZ WLODEK;SMITH STEVEN |
分类号 |
G11C17/00;G11C11/40;G11C11/401;G11C17/16;H01L21/28;H01L21/331;H01L21/336;H01L23/525;H01L27/10;H01L27/115;H01L29/423;H01L29/66;H01L29/78 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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