| 摘要 |
A frequency dividing circuit includes: a D-type flip flop that outputs frequency-divided signal synchronized with input clock and reverse phase signal corresponding to the frequency-divided signal; a variable delay circuit that generates a delay feedback signal delayed by a specific delay time from the reverse phase signal input from the D-type flip flop and feeds back the delay feedback signal to the D-type flip flop; and a delay adjusting circuit that detects a phase difference between the reverse phase signal input from the D-type flip flop and the delay feedback signal input from the variable delay circuit, obtains detected results, and outputs to the variable delay circuit a control signal to perform control so that the delay time becomes time required to ensure setup/hold time of the D-type flip flop, based on the detected results.
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