发明名称 Attaching and virtualizing reconfigurable logic units to a processor
摘要 In one embodiment, the present invention includes a pipeline to execute instructions out-of-order, where the pipeline has front-end stages, execution units, and back-end stages, and the execution units are coupled between dispatch ports of the front-end stages and writeback ports of the back-end stages. Further, a reconfigurable logic is coupled between one of the dispatch ports and one of the writeback ports. Other embodiments are described and claimed.
申请公布号 US2009083518(A1) 申请公布日期 2009.03.26
申请号 US20070903914 申请日期 2007.09.25
申请人 GLEW ANDREW F 发明人 GLEW ANDREW F.
分类号 G06F15/76;G06F9/02 主分类号 G06F15/76
代理机构 代理人
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