发明名称 LAYOUT METHOD, LAYOUT PROGRAM, AND LAYOUT DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To suppress characteristic variations in transistors, which are caused by data densities of gates, in a semiconductor integrated circuit. SOLUTION: An automatic layout device 10 for the semiconductor integrated circuit determines cells to be disposed so that the number of gates existing within a prescribed region around a reference gate 111 already disposed in the vicinity of the boundary between the cells is within a prescribed range, when disposing the cells adjacently in a gate direction. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009065056(A) 申请公布日期 2009.03.26
申请号 JP20070233285 申请日期 2007.09.07
申请人 NEC ELECTRONICS CORP 发明人 KOBAYASHI HISAHIRO
分类号 H01L21/82;G06F17/50 主分类号 H01L21/82
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