PROCESSING ELEMENT (PE) STRUCTURE FORMING FLOATING POINT-RECONFIGURABLE ARRAY (FP-RA) AND FP-RA CONTROL CIRCUIT FOR CONTROLLING THE FP-RA

摘要

Provided is a processing element (PE) structure forming a floating point-reconfigurable array (FP-RA) for FP arithmetic, and an FP-RA control circuit for controlling the same FP-RA, in an FP-RA structure that can support FP arithmetic. The PE structure for integer arithmetic forms an FP-RA supporting FP arithmetic, and PEs are paired to form a floating point unit (FPU)-PE. The PE structure includes an arithmetic logic unit (ALU) performing arithmetic by receiving two operands; two multiplexers (MUXes) each inputting one input value to the ALU; a shifter performing a shift operation on results of the ALU; and a temporary register storing interim results of the ALU and the shifter, and an output register storing final results of the ALU and the shifter, wherein data paths are formed between the above elements for the FP arithmetic.