| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To detect a level of cycle-to-cycle jitter. <P>SOLUTION: A delay signal of an oscillating clock signal (vco) in a PLL circuit (2) is latched at two or more latch circuits (23_1-23_n) in synchronization with variance of two or more delay signals of a reference clock signal (ref). For each latch circuit, its output or its inverse signal is selected by a selector (24_1-24_n). For each selector, the number of times of variance in the output is counted by a counter (25_1-25_n). For every 2n cycle of the oscillating clock signal, if the selection of the last selector is a non-inversion output, and a counter value of the this-time counter is n or more, a control circuit (28) reverses the selection status of the selector. If the selection of the last selector is an inversion output, and the counter value of the this-time counter is n or more, the control circuit (28) reverses the selection status of the selector. The counter value of the primary counter is outputted as for example, a jitter detection information. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
