| 摘要 |
A data driver circuit and a delay-locked loop (DLL) are provided. The data driver circuit and DLL can operate normally in spite of errors, etc., caused when an analog data signal is applied to a display panel. The DLL, which receives a first clock signal and outputs a second clock signal, includes a phase detector for outputting a phase difference signal according to the first clock signal, the second clock signal and at least one delay signal, and a delay line for generating the second clock signal and the delay signal by delaying the first clock signal. Here, the phase difference signal has a value corresponding to a phase difference between the first clock signal and the second clock signal, according to the first clock signal or the second clock signal, and a value corresponding to a case in which there is no phase difference according to the delay signal, and a first delay that is a delay of the second clock signal with respect to the first clock signal changes according to the phase difference signal.
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