| 摘要 |
A semiconductor memory device having a redundancy memory block and a cell array structure thereof, the semiconductor memory device having a plurality of sub-mats constituting a memory cell array, wherein each of the plurality of sub-mats includes a plurality of normal memory blocks of which each includes a plurality of normal memory cells and that are disposed adjacent one another; and at least one redundancy memory block having the same structure as the plurality of normal memory blocks, being disposed adjacent at least one of the plurality of normal memory blocks and having a plurality of redundancy memory cells for a row and column repair, thereby enhancing a redundancy efficiency.
|
