发明名称 |
Methods and apparatuses for designing integrated circuits using virtual cells |
摘要 |
Methods and apparatuses for analyzing and/or designing integrated circuits using virtual transparent cells disclosed. Some embodiments comprise calculating model values for virtual transparent cells or elements of an integrated circuit design varying a transparency variable in modeling equations, and allowing replacement of the cell with a wire based upon the calculations. Varying the value of the transparency value for the calculations may allow the virtual transparent cells to be continuously modeled between a wire and a conventional version of the cell. Some embodiments may comprise a cell library with one or more modeling formulas for one or more virtual transparent cells and a response module to calculate different model values of the modeling formulas.
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申请公布号 |
US2009083681(A1) |
申请公布日期 |
2009.03.26 |
申请号 |
US20070904161 |
申请日期 |
2007.09.26 |
申请人 |
MCCOO MILES F;BIN MICHAEL;LEVY RAN;FRIZUS ZIV |
发明人 |
MCCOO MILES F.;BIN MICHAEL;LEVY RAN;FRIZUS ZIV |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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