| 摘要 |
A self-repairing SRAM and a method for reducing parametric failures in SRAM. On-chip leakage or delay monitors are employed to detect inter-die Vt process corners, in response to which the SRAM applies adaptive body bias to reduce the number of parametric failures in a die and improve memory yield. Embodiments include circuitry for applying reverse body bias (RBB) to the SRAM array in the presence of a low inter-die Vt process corner, thereby reducing possible read and hold failures, and applying forward body bias (FBB) to the array in the presence of a high inter-die Vt process corner, thereby reducing possible access and write failures.
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