发明名称 |
Auto generation of a multi-staged processing pipeline hardware implementation for designs captured in high level languages |
摘要 |
A method of creating a multi-staged hardware implementation based upon a high level language (HLL) program can include generating a language independent model (LIM) from the HLL program, wherein the LIM specifies a plurality of state resources and determining a first and last access to each of the plurality of state resources. The method further can include identifying a plurality of processing stages from the LIM, wherein each processing stage is defined by the first and last access to one of the plurality of state resources. A stall point can be included within the LIM for each of the first accesses. The LIM can be translated into a scheduled hardware description specifying the multi-staged hardware implementation.
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申请公布号 |
US7509619(B1) |
申请公布日期 |
2009.03.24 |
申请号 |
US20050159085 |
申请日期 |
2005.06.22 |
申请人 |
XILINX, INC. |
发明人 |
MILLER IAN D.;HARRIS JONATHAN C. |
分类号 |
G06F17/50;G06F9/44;G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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