发明名称 |
ESD configuration for low parasitic capacitance I/O |
摘要 |
An I/O ESD protection configuration of an integrated circuit that includes an ESD protection circuit connected between an I/O pad and an internal circuit at a first node and to an inductor at a second node. The inductor is connected between the second node and an external power supply. The external power supply provides a high reverse bias voltage across a diode of the ESD protection circuit. An ESD clamp is connected between the second node and a ground. An ESD discharge current is shunted through the ESD protection circuit and through the ESD clamp during a positive I/O ESD event. The inductor can be chosen to tune out a parasitic capacitance of the ESD clamp. The inductor can also block high frequency signals between the I/O pad and the external power supply, thereby minimizing the parasitic capacitance of the diode of the ESD protection circuit at high frequency.
|
申请公布号 |
US7505238(B2) |
申请公布日期 |
2009.03.17 |
申请号 |
US20050174731 |
申请日期 |
2005.07.06 |
申请人 |
WOO AGNES NEVES;CHEN CHUN-YING |
发明人 |
WOO AGNES NEVES;CHEN CHUN-YING |
分类号 |
H02H9/00 |
主分类号 |
H02H9/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|