发明名称 Interconnect structure to reduce stress induced voiding effect
摘要 An interconnect structure that may reduce or eliminate stress induced voids is provided. In an embodiment, a via is formed below a conductive line to provide an electrical connection to an underlying conductive region. The conductive line includes a widened region above the via. The widened region serves to reduce or eliminate stress induced voids between the via and the underlying conductive region. In another embodiment, one or more redundant lines are formed extending from a conductive region, such as a contact pad, such that the redundant line does not electrically couple the conductive region to an underlying conductive region. In a preferred embodiment, the redundant lines extend from a conductive region on a side adjacent to a side having a conductive line coupled to a via.
申请公布号 US7504731(B2) 申请公布日期 2009.03.17
申请号 US20070743499 申请日期 2007.05.02
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 WANG CHIEN-JUNG
分类号 H01L23/48 主分类号 H01L23/48
代理机构 代理人
主权项
地址