| 摘要 |
In a CMOS imager, each cell ( 1 ) comprises a photodiode ( 6 ) which is charged via a reset transistor (T 1 ) before each integration period. During the integration period, the reset transistor is turned off by means of an appropriate gate voltage applied to the gate ( 7 ) of the reset transistor. In order to lower the FPN (fixed pattern noise), this blocking voltage is chosen to be lower than the supply voltage VDD. Surprisingly, it was found that leakage currents could be decreased considerably by this lower blocking voltage, possibly due to lower tunnel currents through the gate oxide which is very thin in modern CMOS processes. In a specific embodiment, said lower blocking voltage can be applied substantially without any limitation of the dynamic range of the imager. |
