Ill-timed logic hazard i.e. single event upset, detecting and correcting architecture for memory register of e.g. aircraft, has elements storing bits of row and column parts calculated on data bits associated to row and column, respectively

摘要

The architecture has memory elements provided for storing data bits (Qi) introduced as script. An additional memory element is provided in a row (Lj) for storing a bit of a row part calculated on data bits associated with the row. Another additional memory element is provided in a column (Ck) for storing a bit of a column part calculated on data bits associated to the column. An error correction unit receives a row part error signal (ErrLj) and a column part error signal (ErrCk) associated to the data bits. Independent claims are also included for the following: (1) a method for testing a memory register (2) a method for detecting an error in a memory register.