发明名称 |
FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL |
摘要 |
A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. The memory system may include dynamic top gate coupling. A programming algorithm and waveforms with top gate handling is included.
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申请公布号 |
US2009067239(A1) |
申请公布日期 |
2009.03.12 |
申请号 |
US20080267519 |
申请日期 |
2008.11.07 |
申请人 |
SILICON STORAGE TECHNOLOGY, INC. |
发明人 |
TRAN HIEU VAN;NGUYEN HUNG QUOC;LY ANH;HSUEH SHENG-HSIUNG;NGUYEN SANG THANH;HOANG LOC B.;CHOI STEVE;VU THUAN T. |
分类号 |
G11C16/00;G11C16/06 |
主分类号 |
G11C16/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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