发明名称 DUMMY PATTERN ARRANGEMENT DEVICE AND DUMMY PATTERN ARRANGEMENT METHOD
摘要 <p><P>PROBLEM TO BE SOLVED: To specify plural kinds of dummy pattern size and dummy pattern arrangement optimal to each area on a chip area by an EB arithmetic operation. <P>SOLUTION: A dummy pattern arrangement device is configured to divide EB data into an area A and other areas, and to cover the area A with a recognition layer having a certain algorithm, and to discriminate a section covered with the recognition layer (recognition layer A) from other section. The dummy patterns in the area A are generated in the same start point in order to arrange the same dummy patterns in the area A, and to create the recognition layer in which the same dummy patterns are arranged even when started from any corner of the area A in order to arrange the same dummy pattern in the area A even when the dummy patterns are arranged with rotation. In the recognition layer, the shapes and interval values of the dummy patterns are the same in the X direction and the Y direction, and the size of the recognition layer A is calculated by (the multiple of (the size+interval value of the dummy pattern))+dummy pattern size, in both the X direction and Y direction. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009053763(A) 申请公布日期 2009.03.12
申请号 JP20070217464 申请日期 2007.08.23
申请人 NEC ELECTRONICS CORP 发明人 KIMOTO TOMOKO
分类号 G06F17/50;H01L21/82;H01L21/822;H01L27/04 主分类号 G06F17/50
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