发明名称 TIMING GENERATING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a circuit technology capable of finely setting transition timing in a relevant level of a processing objective signal which has a constant or a variable period, and is transited at least in two levels during one period. SOLUTION: A timing generation circuit has: (A) a period-signal generating circuit 11 outputting a first period signal, a second period signal, ..., and an M-th period signal; (B) a group of counting circuits 12 comprising first to an M-th counting circuits for counting the first to the M-th period signals; and (C) a setting device 13 for distributing a value of predetermined timing at a temporal axis, representing the distributed value at the temporal axis of the predetermined timing as the number N<SB>1</SB>of the period in the first period signal, the number N<SB>2</SB>of the period in the second period signal, ..., and the number N<SB>M</SB>of the period in the M-th period signal, and setting the number N<SB>1</SB>of the period in the first period signal to the first counting circuit, the number N<SB>2</SB>of the period in the second period signal to the second counting circuit, ..., and the number N<SB>M</SB>of the period in the M-th period signal to the M-th counting circuit. COPYRIGHT: (C)2009,JPO&INPIT
申请公布号 JP2009055597(A) 申请公布日期 2009.03.12
申请号 JP20080159794 申请日期 2008.06.18
申请人 NAGASAKI UNIV 发明人 KUROKAWA FUJIO
分类号 H03K5/00;H03K23/66 主分类号 H03K5/00
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