发明名称 |
Method and apparatus for analyzing digital circuits |
摘要 |
By providing at least two hardware representations of a specified circuit design, an efficient debugging system is provided that allows 100% design visibility at an extremely reduced simulation time owing to a time-shifted operation of the at least two hardware representations. Upon detection of a specified abort state in the leading hardware representation, the corresponding delayed state of the time-shifted hardware representation may be used for a subsequent simulation of only a relevant portion of the test run that has lead to the specified abort state.
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申请公布号 |
US7502969(B2) |
申请公布日期 |
2009.03.10 |
申请号 |
US20040858601 |
申请日期 |
2004.06.01 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
BEARD DOUGLAS RICHARD;EISENREICH HOLGER;EICHHORN KAI |
分类号 |
G06F11/00;G06F17/50 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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