发明名称 |
Error correction apparatus, systems, and methods |
摘要 |
A system comprises a non volatile memory and a plurality of processors. The non volatile memory stores an error handling routine. Each processor of the plurality of processors accesses the error handling routine on detecting an error and, on certain errors, signals the remaining processors to enter a rendezvous state. In the rendezvous state, a single processor takes over and performs error handling.
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申请公布号 |
US7502959(B2) |
申请公布日期 |
2009.03.10 |
申请号 |
US20030628726 |
申请日期 |
2003.07.28 |
申请人 |
INTEL CORPORATION |
发明人 |
MARISETTY SURESH;THANGADURAI GEORGE;AYYAR MANI |
分类号 |
G06F11/00;G06F11/27;G11C7/00 |
主分类号 |
G06F11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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