发明名称 |
Display device and driving method of the same |
摘要 |
Writing of a digital video signal of a lower order bit into a memory is eliminated during a second display mode in which the number of gradations is reduced as compared to in a first display mode of high-level gradation. In addition, read out of the digital video signal of the lower order bit from the memory is also eliminated. The amount of information of a digital image signal inputted to a source signal line driver circuit is reduced. In accordance with such operation, a display controller functions to make start pulses and clock pulses inputted to the source signal line driver circuit have a lower frequency and to lower a driving voltage. When the gradation is reduced, a frame period in the second display mode may be set longer as compared to that in the first display mode, and therefore low electric power consumption is achieved.
|
申请公布号 |
US7502039(B2) |
申请公布日期 |
2009.03.10 |
申请号 |
US20030705827 |
申请日期 |
2003.11.13 |
申请人 |
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. |
发明人 |
KOYAMA JUN;KIMURA HAJIME;YAMAZAKI YU |
分类号 |
G09G3/30;G09G5/10;G09G3/20;G09G3/32;G09G5/36;G09G5/399;H04N5/66 |
主分类号 |
G09G3/30 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|