| 摘要 |
A latch circuit comprising, a differential input with a non-inverting input (D+) and an inverting input (D-). The latch further comprises a differential output with a non-inverting output (Q+) and an inverting output (Q-). One of the outputs (Q-) is coupled to one of the inputs input (D+) having an opposite polarity. The latch further comprises a control input for receiving a control signal (VcM) for determining a threshold for an input signal (In) such that if the input signal is at larger than the threshold the non-inverting output is in a HIGH logic state and in a LOW state if the input signal is smaller than the threshold.
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