RECEIVER CIRCUIT

摘要

A receiver circuit having the noise characteristics of being excellent to simple and small area is provided to reduce the power consumption and include excellent noise characteristic due to implementing equalization at a simple structure. The receiver circuit of a multi-phase clock base is synchronized to a plurality of clocks. The receiver circuit senses and transmits input data. A receiver circuit comprises a sense amplifier(112) and a discharging controlling unit(111). A sense amplifier is synchronized to one clock in first clock among a plurality of clocks. A first signal which amplifies input data and outputted is received the sense amplifier as the offset voltage. The sense amplifier is driven by being synchronized to a second clock which next becomes with the enable of the first clock. And the sense amplifier outputs the second signal. According to the offset voltage, the discharging controlling unit controls the driving rate of the sense amplifier by changing the node potential of the sense amplifier.