发明名称 Phase error correction circuit for a high speed frequency synthesizer
摘要 Circuits, methods, and apparatus for adjusting an NCO output in order to provide a signal that is phase-locked to a reference signal. This is particularly beneficial where the frequencies of the NCO output and reference signal are unrelated. One embodiment provides a circuit that corrects the phase of the NCO output in two steps in order to reduce the chance of metastability. During the first, the output of the NCO is phase shifted to the closest correct portion of a cycle of a clock signal. A second correction is then performed by steering a number of currents under the control of at least some of a number of remainder bits from the NCO. The current steering provides a die area efficient, low-noise phase correction. The decoded remainder bits are latched using a feed forward circuit that prevents the device from entering a locked state.
申请公布号 US7498852(B1) 申请公布日期 2009.03.03
申请号 US20070686356 申请日期 2007.03.15
申请人 INTERSIL AMERICAS INC. 发明人 AGARWAL SANDEEP;CHEN XIAOLE
分类号 H03B21/00 主分类号 H03B21/00
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