| 摘要 |
Equalization techniques in clock recovery receivers may include use of a passive equalizer prior to amplification, combined frequency paths in and active and/or passive equalizer, capacitive degeneration and/or negative feedback with low-pass filtering in an active equalizer, a decision feedback equalizer with multiple decision paths, and programmable tail currents to change switching points. A compensation circuit for a pre/post equalizer may include an oscillator fabricated from replica components to compensate for process variations and a look-up table to provide process variation correction in response to programmed equalizer settings.
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