发明名称 Semiconductor integrated circuit with reduced speed variations
摘要 In a semiconductor integrated circuit of the present invention, the main circuit 2 includes MOS transistors in which the source and the substrate are separated from each other. The substrate potential control circuit 1 controls the substrate potential of the MOS transistors of the main circuit 2 so that the actual saturation current value of the MOS transistors of the main circuit 2 is equal to the target saturation current value Ids under the operating power supply voltage Vdd of the main circuit 2. Therefore, it is possible to suppress variations in the operation speed even if the operating power supply voltage of the semiconductor integrated circuit is reduced.
申请公布号 US7498865(B2) 申请公布日期 2009.03.03
申请号 US20040511165 申请日期 2004.10.14
申请人 PANASONIC CORPORATION 发明人 SAKIYAMA SHIRO;KINOSHITA MASAYOSHI;SUMITA MASAYA
分类号 H03K3/01;G05F1/565;H03K19/003 主分类号 H03K3/01
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