SEMICONDUCTOR MEMORY, AND METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To simply detect performance defect of a sub word decoder in a short period of time. SOLUTION: Each sub word line is connected to a gate of a transfer transistor of a memory cell. A first switch of the sub word decoder connects a sub word line to a high-level voltage line when a main word line is active level. A second switch connects the sub word line to a low-level voltage line when the main word line is inactive. A third switch connects the sub word line to the low-voltage line when a word reset signal line is active. A reset control circuit inhibits non-activation of the main word line or activation of the word reset signal to inhibit the second or third switch from being turned on during a test mode, and can simply detect the performance defect of the sub word decoder in a short period of time by forcibly turning off either the second switch or the third switch. COPYRIGHT: (C)2009,JPO&INPIT