| 摘要 |
A descrambling circuit includes three or more scramble value generators, each configured to generate a new scramble value by a formula at a state of shifting number of times different from each other by every eight bits based on a predetermined generator polynomial, a scramble value generated by the generator polynomial, and a descramble unit configured to descramble partially discontinuous scrambled input data by using the scramble values generated by the three or more scramble value generators.
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