| 摘要 |
A clock pulse generation circuit is provided to prevent an overlapping effect of a clock pulse signal for synchronizing a data signal. A clock pulse generation circuit includes a pulse generation unit(10), a clock control unit(20), and a pre-driving unit(30). The pulse generation unit varies a pulse width of a clock signal in response to an in-phase clock signal(RCLKDLL) and a reversed phase clock signal(FCLKDLL) and outputs the varied clock signal. The clock control unit controls the clock signal in response to the clock signal outputted from the pulse generation unit in order to prevent an overlapping and duty-lowering effect between the clock signals. The pre-driving unit outputs data driving signals(RCLK,FCLK) in response to the clock signal outputted from the clock control unit.
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