发明名称 |
DATA FLOW GRAPH GENERATION DEVICE, SETTING DATA GENERATION DEVICE, PROCESSOR AND DATA FLOW GRAPH GENERATION METHOD |
摘要 |
<P>PROBLEM TO BE SOLVED: To automatically generate a data flow graph corresponding to a reconfigurable processor capable of performing multiple length calculation. <P>SOLUTION: This data flow graph generation device has: an arithmetic bit number determination part determining the number of arithmetic bits necessary for calculation performed in a logic circuit of a reconfigurable circuit; and a node generation part generating a node corresponding to the calculation. The node generation part generates one node corresponding to one piece of calculation when the necessary number of the arithmetic bits is the number of arithmetic bits allowing the calculation or below, and generates a plurality of the nodes correspondingly to the one calculation when the necessary number of the arithmetic bits is larger than the number of the arithmetic bits allowing the calculation. <P>COPYRIGHT: (C)2009,JPO&INPIT |
申请公布号 |
JP2009043027(A) |
申请公布日期 |
2009.02.26 |
申请号 |
JP20070207338 |
申请日期 |
2007.08.09 |
申请人 |
SANYO ELECTRIC CO LTD |
发明人 |
KOSONE MAKOTO;IIZUKA KAZUHISA |
分类号 |
G06F17/50;G06F7/00;G06F9/45 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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