发明名称 CLASS-D AMPLIFIER CIRCUIT
摘要 <p><P>PROBLEM TO BE SOLVED: To attain reduction in distortion when a minute signal is inputted in a class-D amplifier circuit. <P>SOLUTION: An up-down counter 70 outputs such a signal that a delay amount in a delay amount variable circuit 50 becomes large, and such a signal that the delay amount becomes small. Output of the both signals is usually performed alternatively or complementarily. More specifically, the delay amount is gradually increased by the former, and the delay amount is gradually reduced by the latter. Thus, widths of output pulses OutP, OutM gradually increase or gradually decrease. <P>COPYRIGHT: (C)2009,JPO&INPIT</p>
申请公布号 JP2009044380(A) 申请公布日期 2009.02.26
申请号 JP20070206310 申请日期 2007.08.08
申请人 YAMAHA CORP 发明人 KOIDE MASARU;TANAKA TAISHIN;KAWAI HIROKATA;SUZUKI MASAYA
分类号 H03F3/217 主分类号 H03F3/217
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