| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To achieve a memory cell with which no needless areal overhead is produced in a semiconductor integrated circuit even when an advanced manufacturing process is applied thereto. <P>SOLUTION: An information holding circuit 2B is equipped with a first inverting circuit 18A and a second inverting circuit 18B having two homopolar transistors 18c, 18d continuously connected to each other in series. An output of the first inverting circuit 18A is connected to an input of the second inverting circuit 18B, and an output of the second inverting circuit 18B is connected to an input of the first inverting circuit 18A. A write port section AW is connected to the information holding circuit 2B. A data signal of the write port section AW is input to a gate of the transistor 18C which is one of the two homopolar transistors 18c, 18d of the second inverting circuit 18B. <P>COPYRIGHT: (C)2009,JPO&INPIT</p> |
