发明名称 Memory chip architecture with high speed operation
摘要 A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.
申请公布号 US7495991(B2) 申请公布日期 2009.02.24
申请号 US20070999465 申请日期 2007.12.04
申请人 HYNIX SEMICONDUCTOR INC. 发明人 LEE GEUN-IL;JOO YONG-SUK
分类号 G11C8/00 主分类号 G11C8/00
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