摘要 |
<p>A method and computer system for reducing the wiring congestion, required real estate, and access latency in a cache subsystem with a sectored and sliced lower cache by re-configuring sector-to-slice allocation and the lower cache addressing scheme. With this allocation, sectors having discontiguous addresses are placed within the same slice, and a reduced- wiring scheme is possible between two levels of lower caches based on this re-assignment of the addressable sectors within the cache slices. Additionally, the lower cache effective address tag is re-configured such that the address fields previously allocated to identifying the sector and the slice are switched relative to each other's location within the address tag. This re-allocation of the address bits enables direct slice addressing based on the indicated sector.</p> |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION;IBM UNITED KINGDOM LIMITED;CLARK, LEO, JAMES;FIELDS, JAMES, STEPHEN, JR;GUTHRIE, GUY, LYNN;STARKE, WILLIAM, JOHN;WILLIAMS, DEREK, EDWARD;WILLIAMS, PHILIP |
发明人 |
CLARK, LEO, JAMES;FIELDS, JAMES, STEPHEN, JR;GUTHRIE, GUY, LYNN;STARKE, WILLIAM, JOHN;WILLIAMS, DEREK, EDWARD;WILLIAMS, PHILIP |